A ferroelectric memory composed of memory cells each including a ferroelectric capacitor is developed as a semiconductor memory device which has both advantages of DRAMs and flash memories/EEPROMs. The ferroelectric memory operates the ferroelectric capacitor made of ferroelectric material, which is insulating material, as a variable capacitor. The ferroelectric memory can hold data without a power supply, by utilizing residual dielectric polarization which is left even when no voltage is applied to the ferroelectric capacitor.
In recent years, there has been proposed a technique for reading a ferroelectric memory referred to as bit line GND sensing technique. According to this type of reading technique, in order to prevent fluctuation in voltage of bit lines when applying a voltage to plate lines, charges are read out from memory cells to the bit lines and are transferred to charge storing circuits through charge transferring circuits referred to as charge transfers which are formed in pre-sense amplifiers. The amounts of charges transferred to the charge storing circuits are converted to voltages. Then the logical values corresponding to the converted voltages are latched by the sense amplifiers at the predetermined timing, and the logical values of the data retained in the memory cells are read (for example, refer to Japanese Laid-open Patent publication No. 2002-133857).
Further, there has been proposed a technique such that a detection signal is output when output voltages of the pre-sense amplifiers reach a predetermined voltage, and data read from complementary bit lines in synchronization with the detection signal are latched in the sense amplifiers (for example, refer to Japanese Laid-open Patent publication No. 2005-129151).
In general, in the read operation and the write operation of a semiconductor memory, control circuits such as an address decoder, a word driver and a sense amplifier are operated sequentially. Accordingly, for example, timing signals for these control circuits are generated sequentially using cascade-coupled delay circuits. The delay circuits are made of transistors and so on, and thus delay times of the delay circuits disperse due to a variance of manufacturing conditions of the semiconductor memory. On the other hand, changes in voltages read to the bit lines from the memory cells are constant without depending on characteristics of the transistors. Accordingly, for example, when threshold voltages of the transistors are low, it is possible that the sense amplifiers latch data before charges are read sufficiently to the bit lines from the memory cells. When the pre-sense amplifiers are coupled to the bit lines, it is possible that the sense amplifiers latch data before output voltages of the pre-sense amplifiers become sufficiently large. In these cases, the semiconductor memory malfunctions.
Further, the amounts of charges read to the bit lines vary due to, for example, dispersion of manufacturing conditions of memory cell capacitors. For example, when the capacitance values of manufactured capacitors are small, the amounts of charges read to the bit lines become small. With the technique in which a detection signal is generated using pre-sense amplifiers and data are latched in sense amplifiers in synchronization with the detection signal, when output voltages of the pre-sense amplifiers do not reach a predetermined voltage, the detection signal will not be output and hence the sense amplifiers are unable to latch data. When this happens, the semiconductor memory malfunctions.